In solid-state imaging devices typified by complementary metal oxide semiconductor (CMOS) image sensors, the increasing number of pixels has been accompanied by a marked tendency to refine the pixel size. In the case of back-illuminated CMOS image sensors, in particular, various layouts for pixel sharing have been proposed by taking advantage of a high degree of freedom in layout design. The sharing involves, for example, allowing multiple pixels (i.e., their corresponding photodiodes (PDs)) to share a floating diffusion (FD) region and various pixel transistors.
However, the layout of pixel transistors and other components is subject to constraints where the pixel size is refined to approximately 1 μm, for example, even if the above-mentioned pixel sharing technology is used. Specifically, if design is such that the aperture ratio of PDs is maximized to accommodate the increasingly refined pixel size, the area occupied by pixel transistors needs to be reduced correspondingly. In that case, the characteristics such as sensitivity (output) of multiple pixels that share FD regions can become uneven.
In the past, such irregularities have been suppressed using various gates (pixel transistors) with symmetric densities and a symmetric source (S)/drain (D) layout to reduce differences in sensitivity between the pixels sharing FD regions (e.g., see PTL 1).
FIG. 1 illustrates a typical layout of a pixel sharing unit in a back-illuminated CMOS image sensor disclosed by PTL 1, the unit having eight pixels (i.e., their corresponding PDs) sharing two FD regions.
Each pixel sharing unit 110 is made up of a first light receiving section 21, a second light receiving section 22, a first transistor group 31, and a second transistor group 32. The pixel sharing unit 110 further includes a first well contact 23a corresponding to the first light receiving section 21 and a second well contact 23b corresponding to the second light receiving section 22.
The first light receiving section 21 is made up of four PDs 111 to 114, an FD region 16a shared by the PDs 111 to 114, and transfer gates 121a to 124a for connecting each of the PDs 111 to 114 with the FD region 16a. 
Likewise, the second light receiving section 22 is made up of four PDs 115 to 118, an FD region 16b shared by the PDs 115 to 118, and transfer gates 125a to 128a for connecting each of the PDs 115 to 118 with the FD region 16b. 
The first transistor group 31 is made up of an amplifier gate 13a, a selector gate 15a, and S/D regions 31a to 31c. These components form a symmetrical layout in which an S/D region, a pixel transistor, an S/D region, a pixel transistor, and an S/D region are disposed in that order.
The second transistor group 32 is made up of a first reset gate 14a, a second reset gate 14b, and S/D regions 32a to 32c. As with the first transistor group 31, these components form a symmetrical layout in which an S/D region, a pixel transistor, an S/D region, a pixel transistor, and an S/D region are disposed in that order.
Normally, one reset gate would be sufficient. However, the second transistor group 32 is supplemented with a dummy reset gate to ensure layout symmetry with respect to the first transistor group 31. The added dummy reset gate makes the second transistor group 32 as wide as the first transistor group 31 having the same layout.
As illustrated in FIG. 1, the layout of the first light receiving section 21, and first transistor group 31 is symmetrical with respect to the layout of the second light receiving section 22 and second transistor group 32 in the pixel sharing unit 110. This reduces differences in sensitivity (output) between the pixels of the same color in each pixel sharing unit 110.